Memory systems in electronic systems are typically used to store data for retrieval at a later time. Memory systems come in different types of memory. For example, one type of memory is a “volatile” memory, which can store data only when supplied with power. Volatile memory systems are typically designed as dynamic random access memory (DRAM) or static random access memory (SRAM) systems, each having different memory cell configurations. These types of memory systems are often used in computer systems and other processor-based systems for storing data used during processing. Another type of memory system is a “non-volatile” memory system, which can store data even when power is not supplied. There are different designs for non-volatile memory, including NAND-type flash memory and NOR-type flash memory, each having a different memory cell arrangement and manner of accessing data stored by the memory cells. Non-volatile memory systems are used in applications where data should be continuously stored, even when the electronic system including the non-volatile memory is switched off. Cellular phones, digital cameras, personal digital assistants, digital music players, are some examples of where non-volatile memory systems are used.
Memory systems can also be implemented in different forms. For example, a memory system can be implemented as an individual memory device. Individual memory devices can be electrically coupled and mounted together on a common substrate to form a memory module, which is then coupled to an electronic system, such as a computer system. Individual memory devices can also be electrically coupled and mounted to a substrate on which other components of an electronic system are also mounted. Memory systems can also be “embedded” in an electronic system. That is, the memory system is formed on a common semiconductor with other electrical circuitry of an electrical system. As illustrated by the previous discussion, memory systems come in different types and arrangements, and are used in a wide range of electronic systems.
It is generally desirable for a memory system to have fast access times. That is, the less time required to retrieve data from the memory system, the more desirable the memory system. One approach taken to reduce access times of a memory system is to more precisely control internal operation and timing of memory circuitry, such as controlling when signals are driven onto signal lines and when circuitry is activated and deactivated. By precisely controlling the timing and operation, the memory system can provide data from requested memory locations in the least amount of time while still including sufficient timing margin to allow for variations in manufacture and operating conditions that may affect performance of the memory system. However, as with many electrical systems, physical limitations limit the degree of precision for controlling operation of the memory system. One example is electrical loading of a signal line. As known, electrical loading is generally greater for longer signal lines. Electrical loading is also affected by the number of circuit elements coupled to the signal line. Where a signal is propagated over a relatively long signal line, or a signal line that is coupled to many circuit elements, the deterioration of signal response and resulting delay in a signal driven onto the signal line must be taken into account. Typically, the “worst case” timing is used as the basis for determining operation and internal timing of the memory system. Using the worst case timing results in an access time that is typically greater than what could be achieved with more precise control over internal operation and timing. It is also generally desirable for a memory system to have low power consumption and small form factor. These factors often compete with one another, and the resulting design of a memory system is a compromise of the various considerations.
Therefore, there is a need for alternative approaches in memory array architecture that provide more precise control over internal operation and timing, while also reducing power consumption and layout size of memory systems without compromising memory system performance.